Arithmetic // SRL (Shift Right Logical)
The contents of operand m are shifted right 1 bit position. The contents of bit 0 are copied to the Carry flag, and bit 7 is reset. Bit 0 is the least-significant bit.
Register B contains the following data. 76534 2 10 10010 1 11 Upon the execution of an SRL B instruction, Register B and the Carry flag now contain: 76534 2 10C 1 001 0 0 11 1
srl b 0xCB38,
2 bytes, 8Tsrl c 0xCB39,
2 bytes, 8Tsrl d 0xCB3A,
2 bytes, 8Tsrl e 0xCB3B,
2 bytes, 8Tsrl h 0xCB3C,
2 bytes, 8Tsrl l 0xCB3D,
2 bytes, 8Tsrl (hl) 0xCB3E,
2 bytes, 15Tsrl a 0xCB3F,
2 bytes, 8Tsrl (ix+*),b 0xDDCB**38,
4 bytes, 23Tsrl (ix+*),c 0xDDCB**39,
4 bytes, 23Tsrl (ix+*),d 0xDDCB**3A,
4 bytes, 23Tsrl (ix+*),e 0xDDCB**3B,
4 bytes, 23Tsrl (ix+*),h 0xDDCB**3C,
4 bytes, 23Tsrl (ix+*),l 0xDDCB**3D,
4 bytes, 23Tsrl (ix+*) 0xDDCB**3E,
4 bytes, 23Tsrl (ix+*),a 0xDDCB**3F,
4 bytes, 23Tsrl (iy+*),b 0xFDCB**38,
4 bytes, 23Tsrl (iy+*),c 0xFDCB**39,
4 bytes, 23Tsrl (iy+*),d 0xFDCB**3A,
4 bytes, 23Tsrl (iy+*),e 0xFDCB**3B,
4 bytes, 23Tsrl (iy+*),h 0xFDCB**3C,
4 bytes, 23Tsrl (iy+*),l 0xFDCB**3D,
4 bytes, 23Tsrl (iy+*) 0xFDCB**3E,
4 bytes, 23Tsrl (iy+*),a 0xFDCB**3F,
4 bytes, 23T