srl (iy+)*

Arithmetic // SRL (Shift Right Logical)

0xFDCB**3E - u64971

Description

The contents of the memory location pointed to by iy plus * are shifted right one bit position. The contents of bit 0 are copied to the carry flag and a zero is put into bit 7.

T States	Bytes
23	4

Condition Bits Affected

S affected as defined
Z affected as defined
H reset
P/V detects parity
N reset
C affected as defined

source

{
  "flags": {
    "S": "affected as defined",
    "Z": "affected as defined",
    "H": "reset",
    "P/V": "detects parity",
    "N": "reset",
    "C": "affected as defined"
  },
  "operation": "srl (iy+*)",
  "opcode": "srl",
  "operand": [
    "(iy+*)"
  ],
  "code": "FDCB**3E",
  "bytes": 4,
  "time": 23,
  "description": "The contents of the memory location pointed to by iy plus * are shifted right one bit position. The contents of bit 0 are copied to the carry flag and a zero is put into bit 7.",
  "category": "Arithmetic",
  "subCategory": "SRL (Shift Right Logical)"
}