/opcodes/res

Description

Bit b in operand m is reset.

Example

Upon the execution of a RES 6, D instruction, bit 6 in register 0 is reset. Bit 0 in the D Register is the least-significant bit. Jump Group The following jump group instructions are each described in this section. Simply click to jump to an instruction’s description to learn more. JP nn – see page 262 JP cc, nn – see page 263 JR e – see page 265 JR C, e – see page 267 JR NC, e – see page 269 JR Z, e – see page 271 JR NZ, e – see page 273 JP (HL) – see page 275 JP (IX) – see page 276 JP (IY) – see page 277 DJNZ, e – see page 278

Opcodes