The contents of the HL register pair are placed on the address bus to select a location in memory. The byte contained in this memory location is temporarily stored in the CPU. Then, after the byte counter (B) is decremented, the contents of Register C are placed on the bottom half (A0 through A7) of the address bus to select the I/O device at one of 256 possible ports. Register B can be used as a byte counter, and its decremented value is placed on the top half (A8 through A15) of the address bus at this time. Next, the byte to be output is placed on the data bus and written to the selected peripheral device. Finally, the register pair HL is decremented.


If Register C contains 07h, Register B contains 10h, the HL register pair contains 1000h, and memory location 1000h contains 59h, then upon the execution of an OUTD instruc- tion, Register B contains 0Fh, the HL register pair contains 0FFFh, and byte 59h is writ- ten to the peripheral device mapped to I/O port address 07h.