/opcodes/indr

Description

The contents of Register C are placed on the bottom half (A0 through A7) of the address bus to select the I/O device at one of 256 possible ports. Register B is used as a byte coun- ter, and its contents are placed on the top half (A8 through A15) of the address bus at this time. Then one byte from the selected port is placed on the data bus and written to the CPU. The contents of the HL register pair are placed on the address bus and the input byte is written to the corresponding location of memory. Then HL and the byte counter are dec- remented. If decrementing causes B to go to 0, the instruction is terminated. If B is not 0, the Program Counter is decremented by two and the instruction repeated. Interrupts are recognized and two refresh cycles are executed after each data transfer. When B is set to 0 prior to instruction execution, 256 bytes of data are input. If B ≠ 0:

Example

Register C contains 07h, Register B contains 03h, the HL register pair contains 1000h and the following sequence of bytes is available at the peripheral device mapped to I/O port address 07h: 51h A9h 03h Upon the execution of an INDR instruction, the HL register pair contains 0FFDh, Register B contains a 0, and the memory locations contain the following data: 0FFEh 03h 0FFFh A9h 1000h 51h

Opcodes