/opcodes/cpir

Description

The contents of the memory location addressed by the HL register pair is compared with the contents of the Accumulator. During a compare operation, a condition bit is set. HL is incremented and the Byte Counter (register pair BC) is decremented. If decrementing causes BC to go to 0 or if A = (HL), the instruction is terminated. If BC is not 0 and A ≠ (HL), the program counter is decremented by two and the instruction is repeated. Inter- rupts are recognized and two refresh cycles are executed after each data transfer. If BC is set to 0 before instruction execution, the instruction loops through 64 KB if no match is found. For BC ≠ 0 and A ≠ (HL):

Example

If the HL register pair contains 1111h, the Accumulator contains F3h, the Byte Counter contains 0007h, and memory locations contain the following data. (1111h) contains 52h (1112h) contains 00h (1113h) contains F3h Upon the execution of a CPIR instruction, register pair HL contains 1114h, the Byte Counter contains 0004h, the P/V flag in the F Register is set, and the Z flag in the F Reg- ister is set.

Opcodes