/opcodes/cpdr

Description

The contents of the memory location addressed by the HL register pair is compared with the contents of the Accumulator. During a compare operation, a condition bit is set. The HL and Byte Counter (BC) Register pairs are decremented. If decrementing allows the BC to go to 0 or if A = (HL), the instruction is terminated. If BC is not 0 and A = (HL), the program counter is decremented by two and the instruction is repeated. Interrupts are rec- ognized and two refresh cycles execute after each data transfer. When the BC is set to 0, prior to instruction execution, the instruction loops through 64 KB if no match is found. For BC ≠ 0 and A ≠ (HL):

Example

The HL register pair contains 1118h, the Accumulator contains F3h, the Byte Counter contains 0007h, and memory locations contain the following data. (1118h) contains 52h (1117h) contains 00h (1116h) contains F3h Upon the execution of a CPDR instruction, register pair HL contains 1115h, the Byte Counter contains 0004h, the P/V flag in the F Register is set, and the Z flag in the F Reg- ister is set. 8-Bit Arithmetic Group The following 8-bit arithmetic group instructions are each described in this section. Sim- ply click to jump to an instruction’s description to learn more. ADD A, r – see page 145 ADD A, n – see page 147 ADD A, (HL) – see page 148 ADD A, (IX + d) – see page 149 ADD A, (IY + d) – see page 150 ADC A, s – see page 151 SUB s – see page 153 SBC A, s – see page 155 AND s – see page 157 OR s – see page 159 XOR s – see page 161 CP s – see page 163 INC r – see page 165 INC (HL) – see page 167 INC (IX+d) – see page 168 INC (IY+d) – see page 169 DEC m – see page 170

Opcodes