The contents of the memory location addressed by the HL register pair is compared with the contents of the Accumulator. During a compare operation, a condition bit is set. The HL and Byte Counter (register pair BC) are decremented.
If the HL register pair contains 1111h, memory location 1111h contains 3Bh, the Accu- mulator contains 3Bh, and the Byte Counter contains 0001h. Upon the execution of a CPD instruction, the Byte Counter contains 0000h, the HL register pair contains 1110h, the flag in the F Register is set, and the P/V flag in the F Register is reset. There is no effect on the contents of the Accumulator or address 1111h.